8:1 Multiplexer Virtual Laboratory

PrayogSetu — Interactive Digital Electronics Experiment
Digital Electronics
EXPERIMENT MODE:
🎛️ Digital Input Controls (8 Data + 3 Select Lines)
📁 Data Inputs (I0 – I7)
I0Ch 0
I1Ch 1
I2Ch 2
I3Ch 3
I4Ch 4
I5Ch 5
I6Ch 6
I7Ch 7
⚙️ Select Lines (S2, S1, S0)
S2MSB (Bit 2)
S1Mid (Bit 1)
S0LSB (Bit 0)
💡 Output & Selection Indicator MANUAL MODE
Selected Input I0
Select Value 000
Selected Data Value 0
Output Value (Y) 0
Multiplexer Output LED
LOGIC 0 (OFF)
⚡ 8:1 Multiplexer Gate-Level Schematic Diagram Interactive Signal Animation & Wire Highlighting
S2 S2̅ S1 S1̅ S0 S0̅ S2: 0 S1: 0 S0: 0 NOT NOT NOT I0: 0 I1: 0 I2: 0 I3: 0 I4: 0 I5: 0 I6: 0 I7: 0 AND0 AND1 AND2 AND3 AND4 AND5 AND6 AND7 OR Y: 0 8:1 MULTIPLEXER SELECTED CHANNEL: I0 I0: 0 I0 I1: 0 I1 I2: 0 I2 I3: 0 I3 I4: 0 I4 I5: 0 I5 I6: 0 I6 I7: 0 I7 S2: 0 S2 S1: 0 S1 S0: 0 S0 Y Y: 0
🔍 Binary Data Demonstration & AND Gate Terms
AND0 Output I0 · S2̅ · S1̅ · S0̅ 0
AND1 Output I1 · S2̅ · S1̅ · S0 0
AND2 Output I2 · S2̅ · S1 · S0̅ 0
AND3 Output I3 · S2̅ · S1 · S0 0
AND4 Output I4 · S2 · S1̅ · S0̅ 0
AND5 Output I5 · S2 · S1̅ · S0 0
AND6 Output I6 · S2 · S1 · S0̅ 0
AND7 Output I7 · S2 · S1 · S0 0
Signal Flow Status: Select lines enable a specific AND gate path to route data to output Y.
📊 8:1 Multiplexer Selection Truth Table
Select S2 Select S1 Select S0 Selected Channel Channel Data Value Multiplexer Output (Y)
0 0 0 I0 0 0
0 0 1 I1 0 0
0 1 0 I2 0 0
0 1 1 I3 0 0
1 0 0 I4 0 0
1 0 1 I5 0 0
1 1 0 I6 0 0
1 1 1 I7 0 0
📚 Educational Panel: 8:1 Multiplexer Concepts & Theory

What is an 8:1 Multiplexer?

An 8:1 Multiplexer (MUX), also known as a data selector, is a combinational logic circuit designed to switch one of 8 data inputs (I0 through I7) to a single output line (Y) based on the binary state of 3 select control lines (S2, S1, S0).

Why 3 Select Lines?

To address and select one distinct channel out of N = 8 data inputs, the circuit requires m select lines such that:

2m ≥ N ⇒ 23 = 8 ⇒ m = log2(8) = 3

The 3 select lines form a 3-bit binary number (S2S1S0) ranging from 000 (010) to 111 (710), uniquely identifying which input line is connected to output Y.

Sum of Products (SOP) Boolean Expression

The gate-level logic implements the Boolean equation:

Y = I0·S̅2·S̅1·S̅0 + I1·S̅2·S̅1·S0 + I2·S̅2·S1·S̅0 + I3·S̅2·S1·S0 + I4·S2·S̅1·S̅0 + I5·S2·S̅1·S0 + I6·S2·S1·S̅0 + I7·S2·S1·S0

Multiplexer Hierarchy & Scaling

Multiplexers scale logarithmically in select line count as input capacity doubles:

Multiplexer Type Data Inputs (N) Select Lines (m) Formula
2:1 MUX 2 (I0..I1) 1 (S0) m = log2(2) = 1
4:1 MUX 4 (I0..I3) 2 (S1, S0) m = log2(4) = 2
8:1 MUX (Current) 8 (I0..I7) 3 (S2, S1, S0) m = log2(8) = 3
16:1 MUX 16 (I0..I15) 4 (S3..S0) m = log2(16) = 4

Key Applications

  • Data Routing: Connecting multiple peripheral sensors or data channels to a single ADC/microcontroller pin.
  • CPU Data Bus Selection: Internal register routing and instruction operand selection inside microprocessors.
  • Communication Systems: Time-Division Multiplexing (TDM) to send multiple data streams over a single transmission channel.
  • Signal Switching & Function Generators: Hardware implementation of arbitrary Boolean logic functions without discrete gates.